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Compact high-speed single-bit error-correction circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Compacting circuit responses

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Compacting circuit responses

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Compacting circuit responses

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Comparable circuits for parallel testing DRAM device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Comparator circuit for semiconductor test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Comparator for semiconductor testing device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Compare circuit receiving scan register and inverted clock...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Comparison circuit and method for verification of scan data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Compensating for errors received in a signal

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Compilable address magnitude comparator for memory array...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Compilable address magnitude comparator for memory array...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Compilable memory structure and test methodology for both...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Compilable memory structure and test methodology for both...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Compilation of calibration information for plural testflows

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Complementary logic error detection and correction

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Complementary methods for interleaving and deinterleaving...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Compliance of master-slave modes for low-level debug of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Compliance testing through test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Component testing and recovery

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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