Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-02-09
2000-01-18
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
327 68, G01R 3128, H01H 6100
Patent
active
060165669
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to a comparator circuit to be used in a semiconductor test system for comparing differential output signals of a semiconductor device under test (DUT).
BACKGROUND OF THE INVENTION
In testing differential output signals of DUT, there are two test items. In the first test item, it is tested whether each of the output signals is proper or not (single output test), and in the second test item, it is tested whether the differential output signals as a whole are proper or not (differential output test). This invention relates to the second test item to determine whether the differential output signals are working properly.
The number of semiconductor devices (DUTs) to be operated with small signal levels is increasing these days. These small signal DUTs often have an interface of balanced transmission drive. Accordingly, more detailed quality test is required to evaluate DUTs which function under the balanced transmission condition.
FIG. 6 shows a circuit configuration of a comparator circuit 90 in the conventional technology for one channel of a semiconductor test system. The comparator circuit 90 compares differential output signals, i.e., balanced transmission signals from DUT 100 by comparators 71 and 72 separately provided from one another, upon receiving the differential output signals 101 and 102, respectively.
In this circuit configuration, the low/high evaluation of the DUT differential output signals is made through logic comparison in the comparators with predetermined reference voltages VO81 and VO82 given to the corresponding comparators 71 and 72. The reference voltages VO81 and VO82 are variable voltages for defining threshold voltages of the comparators. Strobe signals 61 and 62 are provided to the comparators to define comparison timings by the comparators 71 and 72.
As a first example, the DUT output waveform is shown in FIG. 5(a). When a common mode peak is generated by the effects such as noise or other causes, the peak will be detected as an abnormal signal at the output of one of the comparators.
When this kind of DUT output waveform is generated, DUT is judged as defective in the single output test wherein only one of the output signals is evaluated. However, under the differential output situation, such a common mode noise is sometimes considered non-defective in a practical use. Thus, a quality test in this differential signal mode is necessary with more precise and detailed test capability.
However, in the conventional test method, the differential output test is difficult to perform, and DUTs are frequently determined as defective even though the DUTs should be acceptable.
FIG. 5(b) shows a second example of differential output signals where the DUT output signals have a relatively large transition timing difference from one another. In such a situation, an accurate timing of the cross point of the differential output signals may not be detected since there is a time difference between an actual transition timing T90 and the output timings T91 and T92 which are the comparison results from both of the comparators. Thus, in the conventional technology, unwanted test results are sometimes produced.
As explained above, because of the circuit configuration of the conventional technology that logically compares the differential output signals 101 and 102 by each separate comparator, unwanted test results arise. For example, when the output signal level is small or when there is much noise, a comparison result will be attained which does not accurately reflect the high/low level or the transition timing of the differential output signals.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a comparator circuit for differential output signals which is not affected by common mode signals by establishing a special comparator circuit of a differential receiver type to meet the requirements for testing the DUT differential output signals.
FIG. 1 shows a first solution according to the present invention.
In ord
REFERENCES:
patent: 5210527 (1993-05-01), Smith et al.
patent: 5436559 (1995-07-01), Takagi et al.
Advantest Corp.
Cady Albert De
Chase Shelly A.
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