Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-02-27
2007-02-27
Whitmore, Stacy A (Department: 2825)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000
Reexamination Certificate
active
10107628
ABSTRACT:
Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.
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Kim Kee Sup
Mitra Subhasish
Intel Corporation
Trop Pruner & Hu P.C.
Whitmore Stacy A
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