Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-22
2008-07-22
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
10906147
ABSTRACT:
A memory structure configured for supporting multiple test methodologies includes a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is further configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, thereby facilitating observation of the memory logic connection at the customer chip, wherein test elements of the memory structure comprise a scan architecture of a first type, and test elements of the customer chip comprise a scan architecture of a second type.
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Eustis Steven M.
Monzel James A.
Oakland Steven F.
Ouellette Michael R.
Cantor & Colburn LLP
LeStrange Michael J.
Ton David
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