Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-10-17
2010-10-12
Whitmore, Stacy A (Department: 2825)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S726000, C714S742000, C716S030000
Reexamination Certificate
active
07814383
ABSTRACT:
Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.
REFERENCES:
patent: 4241307 (1980-12-01), Hong
patent: 6763488 (2004-07-01), Whetsel
patent: 6950974 (2005-09-01), Wohl et al.
patent: 7051257 (2006-05-01), Whetsel
patent: 2003/0115521 (2003-06-01), Rajski et al.
patent: 2003/0131298 (2003-07-01), Rajski et al.
patent: 2005/0097419 (2005-05-01), Rajski et al.
Kim Kee Sup
Mitra Subhasish
Trop Pruner & Hu P.C.
Whitmore Stacy A
LandOfFree
Compacting circuit responses does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Compacting circuit responses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compacting circuit responses will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4182168