Complementary logic error detection and correction

Details Complementary logic error detection and correction Complementary logic error detection and correction

1999-03-15

2002-12-31

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C326S121000, C326S129000

Reexamination Certificate

active

06502220

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to a system and method for ensuring that a complementary condition is maintained at the output of a complementary logic circuit. In particular, the present invention relates to a system and method that automatically corrects an illegal non-complementary condition at the output of a complementary logic circuit, thereby avoiding the unpredictability and uncertainty that result from a non-complementary output.
DESCRIPTION OF THE RELATED ART
As electronic circuit geometries decrease, testing for manufacturing defects becomes increasingly difficult. Many defects can be detected during manufacturing tests. However, some defects, such as resistive shorts between nets, resistive open contacts or excessive transistor leakage, cause only subtle effects that may not cause logical failure during an initial manufacturing test, but will cause failures at a later time. Quiescent power supply current (IDDq) testing has been utilized in the past to detect some of these subtle defects, but in deep sub-micron technologies, normal leakage currents are sufficiently high that it is becoming impossible to detect and identify small amounts of extra current caused by a defect.
Burn-in testing has been utilized in the past to accelerate early-life failures, but today's deep sub-micron technologies are less capable of tolerating the high voltage and temperature conditions utilized in burn-in testing. These trends mean that electronic circuit initial quality and long-term reliability are decreasing, thus forming a need for improved methods of defect detection and error correction to improve initial quality, and to make circuits more fault tolerant in operation.
As processor speeds climb, circuit designers are challenged to achieve higher circuit speeds to accommodate the demand. Techniques such as dynamic logic are suitable for such applications, but are susceptible to performance degradation due to subtle design and manufacturing defects such as noise coupling, charge sharing, and high leakage. Furthermore, debugging dynamic logic is a complex and costly task. Consequently, fast static logic families are becoming more prevalent in the industry today to counteract the difficult design issues that arise in dynamic logic. Also, with the advent of Silicon-On-Insulator (SOI) technologies, with its relatively low capacitive loading and the ability to increase the number of devices in series (“stack height”), static pass-gate logic is becoming very competitive with dynamic logic in circuit speed. In previous BULK CMOS technologies, the traditional limit on series N-type MOSFETs, commonly referred to in the art as “nfets”, (the combination of transistors I
1
and I
3
or I
1
and I
4
of
FIG. 1
) has been two to three. However, in the newer SOI technologies, the limit on series nfets is climbing rapidly, and has already exceeded six. This trend is made possible by two advantageous characteristics of SOI technology: the device threshold dependency on the source-body voltage is removed; and the device diffusion capacitance is lowered by more than 66%.
Many of the fast static pass-gate logic families that are being utilized are complementary in nature, meaning that they produce both true and complement output signals, and circuit input signals are provided in both true and complement form. Examples of such families are Double Pass-transistor Logic (DPL), Differential Cascode Voltage Switch with Pass-Gate (DCVSPG), Complementary Pass-Transistor Logic (CPL), etc.
CPL circuits may be further categorized as belonging to one of two sub-classes: standard and cross-coupled.
FIG. 1A
depicts a prior art three way XOR/XNOR standard CPL circuit
100
, while
FIG. 1B
illustrates a sample three way XOR/XNOR cross-coupled CPL circuit
150
. Note in
FIG. 1A
that standard CPL circuit
100
utilizes small pmos feedback devices
110
and
112
from XOR output
102
and XNOR output
104
to internal node
106
and internal node
108
(TREE_T/TREE_C). Feedback devices
110
and
112
serve to draw the internal nodes
106
and
108
to full rail (up to VDD from VDD-VT). However, note that cross-coupled CPL circuit
150
, of
FIG. 1B
, utilizes similar pmos devices
110
and
112
, connected to complementary internal nodes
106
and
108
(TREE_T/TREE_C), which serve not only to draw the internal nodes full-rail but also increases circuit performance.
Note that in complementary logic circuits
100
and
150
of
FIGS. 1A and 1B
, input signals A
114
and A_
116
are logical complements of each other, as are signal pairs B/B
—
and C/C_. CPL, DCVSPG, and DPL circuits operate differentially. That is, when the input signals force one output high, the associated complementary output is forced low.
However, when a defect occurs in manufacturing or if a defect appears during circuit use, these outputs may no longer be complementary. When this happens, the circuits downstream of this defective circuit no longer see complementary input signals. These “illegal” input states can cause floating nodes (high-impedance, Z state) or value contention (1 and 0 driving onto a net simultaneously, for example) which will produce unpredictable circuit behavior. Thus, such a defect may not be detected during manufacturing testing. For example, if the A/A_ input signals in
FIG. 1B
are simultaneously at a non-complementary 0/0 state due to a defect in the circuit producing signals A/A_, nets TREE_T and TREE_C may be floating (undriven, high impedance) except for cross-coupled pfet devices
110
and
112
. The values that will emerge at nodes
106
and
108
are unpredictable, thus making XOR output
102
and XNOR output
104
unpredictable. Likewise, if input signals A/A
—
are simultaneously at a non-complementary 1/1 state due to a defect, nodes
106
and
108
(TREE_T and TREE_C) will be driven by contending high and low voltage values regardless of the values on the B and C input signals. The resultant voltages on nodes
106
and
108
may be at some value between the high and low voltage states for logic 1 and 0, thus causing complementary XOR/XNOR outputs
102
and
104
to be unpredictable. Most defects that cause an incorrect value at a single output of a complementary pass-gate circuit family will cause unpredictable behavior in downstream circuits, and are thus difficult to detect and identify during testing.
It would therefore be desirable to be able to automatically correct an illegal non-complementary output from a complementary logic circuit during circuit testing and use. Further, it would be desirable to provide a system and method for selectively decoupling one transistor tree within a complementary logic circuit and utilize the other tree to ensure a complementary condition at the output of a complementary logic circuit. Such a system and method, if implemented, would be useful by ensuring that a defect in a complementary logic circuit that would normally cause a non-complementary output may be overridden during runtime circuit operation, thus enhancing chip reliability and manufacturing yield.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a system and method for ensuring that a complementary condition is maintained at the output of a complementary logic circuit.
It is another object of the present invention to provide a system and method for automatically correcting an illegal non-complementary condition at the output of a complementary logic circuit, thereby avoiding the unpredictability and uncertainty that result from a non-complementary output.
Some or all of the foregoing objects may be achieved in one embodiment of the present invention as is now described. A system and method for detecting and rectifying a proscribed non-complementary output from a complementary logic circuit is disclosed. A complementary logic circuit having a true tree and a complement tree is provided. The true tree produces a true signal utilized to generate a true output signal from the complementary logic circuit. The complement tree produces a com

Affiliated with

Also associated with

Rating

Complementary logic error detection and correction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Complementary logic error detection and correction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary logic error detection and correction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2995584