Compact high-speed single-bit error-correction circuit

Details Compact high-speed single-bit error-correction circuit Compact high-speed single-bit error-correction circuit

2004-11-29

2009-06-09

Baker, Stephen M (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S759000

Reexamination Certificate

active

07546510

ABSTRACT:
A compact high-speed data encoder/decoder for single-bit forward error-correction, and methods for same. This is especially useful in situations where hardware and software complexity is restricted, such as in a monolithic flash memory controller during initial startup and software loading, where robust hardware and software error correction is not feasible, and where rapid decoding is important. The present invention arranges the data to be protected into a rectangular array and determines the location of a single bit error in terms of row and column positions. So doing greatly reduces the size of lookup tables for converting error syndromes to error locations, and allows fast error correction by a simple circuit with minimal hardware allocation. Use of square arrays reduces the hardware requirements even further.

REFERENCES:
patent: 5224106 (1993-06-01), Weng
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Fuja, T., et al., “Linear Sum Codes for Random Access Memories”, IEEE transactions on Computers, vol. 37, No. 9, Sep. 1988, pp. 1030-1042.
Gaitanis, G., “TSC-error C/D circuits for SEC/DED product codes”, IEE Proceedings, vol. 135, Pt. E, No. 5, Sep. 1988, pp. 253-356.
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Seguin et al., “A Triple Error-Correcting Product Code for Byte-Oriented Information Systems”, Proceedings of the IEE, vol. 73, No. 11, Nov. 1995, pp. 1683-1684.
Litwin et al., “Linear Block Codes”, IEEE Potentials Magazine, Feb./Mar. 2001, pp. 29-31.
New Parity Retransmission System Using Product Codes R.H. Deng IEE Proceedings vol. 140 No. 5 Oct. 1993 pp. 351-356.
TSC Error C/D Circuits for SEC/DED Product Codes N. Gaitanis IEE Proceedings vol. 135 pt E. No. 5 Sep. 5, 1988 pp. 253-258.
Linear Sum Codes for Random Access Memories Tom Fuja ,Chris Heegard, Rod Goodman, Members of IEEE 1998 IEEE pp. 1030-1042.
Error-Free Coding Peter Elias Dept of Electrical Engineering and Research Laboratory of Electronics MIT Cambridge Massachusetts pp. 29-37.

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