Skipping clock interrupts during system inactivity to reduce pow
Slew rate selection circuit for a programmable device
Soft core control of dedicated memory interface hardware in...
Soft core control of dedicated memory interface hardware in...
Soft core control of dedicated memory interface hardware in...
Software programmable logic using spin transfer torque...
Software programmable logic using spin transfer torque...
Spare cell architecture for fixing design errors in...
Split FIFO configuration of block RAM
Staggered I/O groups for integrated circuits
State splitting for level reduction
Static memory cell circuit with single bit line and...
Stored and combinational logic function generator without dedica
Structure and method for arithmetic function implementation in a
Structure and method for configuration of a field programmable g
Structure and method for implementing hierarchical routing pools
Structure and method for reading blocks of data from selectable
Structure for optionally cascading shift registers
Structure for reducing leakage current in submicron IC devices
Structured integrated circuit device