Split FIFO configuration of block RAM

Details Split FIFO configuration of block RAM Split FIFO configuration of block RAM

2006-09-12

2006-09-12

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S046000

Reexamination Certificate

active

07106098

ABSTRACT:
A programmable logic device includes a block random access memory (“BRAM”) that is split into two first in, first out (“FIFO”) memory arrays. Two sets of FIFO control logic and FIFO ports are associated with a single BRAM so that the BRAM can be operated as memory buffers for two independent FIFO memory systems.

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U.S. Appl. No. 10/838,958, filed May 4, 2004, Zack et al.
U.S. Appl. No. 10/838,957, filed May 4, 2004, Lowe et al.

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