Staggered I/O groups for integrated circuits

Details Staggered I/O groups for integrated circuits Staggered I/O groups for integrated circuits

2011-04-26

2011-04-26

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S101000

Reexamination Certificate

active

07932744

ABSTRACT:
An I/O scheme for an integrated circuit includes a group layout cell. The group layout cell includes a plurality of signal I/O pads. A driver circuit is coupled to each signal I/O pad. The group layout cell also includes two I/O driver-circuit power-supply pads. ESD protection circuitry is coupled to the plurality of driver circuits. The signal I/O pads and the I/O driver-circuit power-supply pads are arranged in rows. The rows may be regular or staggered.

REFERENCES:
patent: 5838627 (1998-11-01), Tomishima et al.
patent: 5962926 (1999-10-01), Torres et al.
patent: 6717270 (2004-04-01), Downey et al.
patent: 6836026 (2004-12-01), Ali et al.
patent: 2006/0022705 (2006-02-01), Or-Bach et al.
patent: 2006/0255477 (2006-11-01), Kim et al.

Affiliated with

Also associated with

Rating

Staggered I/O groups for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Staggered I/O groups for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Staggered I/O groups for integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2720611