Structure and method for implementing hierarchical routing pools

Details Structure and method for implementing hierarchical routing pools Structure and method for implementing hierarchical routing pools

1993-09-01

1995-02-28

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 326 21, 326 93, H03K 19177

Patent

active

053940334

ABSTRACT:
A programmable logic device has multiple groups of generic logic blocks. Each group of generic logic blocks is interconnected by a local routing pools. A global routing pool is provided to interconnect the local routing pools. The global and local routing pools can be implemented in volatile or non-volatile technology, such as E.sup.2 PROM technology. The programmable logic device can also be implemented as an in-system programmable logic device.

REFERENCES:
patent: 4642487 (1987-02-01), Carter
patent: 5225719 (1993-06-01), Agrawal et al.
patent: 5323069 (1994-06-01), Smith, Jr.

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