Structure and method for reading blocks of data from selectable

Details Structure and method for reading blocks of data from selectable Structure and method for reading blocks of data from selectable

1996-09-04

1998-08-04

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

365236, H03K 738

Patent

active

057899380

ABSTRACT:
A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.

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