Structure and method for arithmetic function implementation in a

Details Structure and method for arithmetic function implementation in a Structure and method for arithmetic function implementation in a

1996-10-04

1998-10-13

Nelms, David C.

Electronic digital logic circuitry

Multifunctional or programmable

Array

H03K 19177

Patent

active

058217746

ABSTRACT:
An EPLD having improved routing and arithmetic function implementation characteristics. Cascade and carry logic in macrocells allows for rapid implementation of arithmetic functions without unnecessarily tying up device processing and interconnect resources or unnecessarily delaying processing.

REFERENCES:
patent: 5121006 (1992-06-01), Pedersen
patent: 5350954 (1994-09-01), Patel
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5359242 (1994-10-01), Veenstra
patent: 5450608 (1995-09-01), Steele
patent: 5565792 (1996-10-01), Chiang et al.

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