Soft core control of dedicated memory interface hardware in...

Electronic digital logic circuitry – Multifunctional or programmable – Array

Reexamination Certificate

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Details

C326S037000, C365S232000

Reexamination Certificate

active

11530708

ABSTRACT:
The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.

REFERENCES:
patent: 6806733 (2004-10-01), Pan et al.
patent: 6940768 (2005-09-01), Dahlberg et al.

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