Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1994-10-07
1995-09-12
Hudspeth, David R.
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 8, 326 44, H03K 3356
Patent
active
054500222
ABSTRACT:
A structure and method for configuring a field programmable gate array (FPGA). A configuration memory cell within the FPGA receives a programming signal. In response, the configuration memory cell provides a signal to a configuration control circuit to configure the FPGA. The configuration memory cell includes an input lead, a storage device and a selectable configuration circuit. The input lead carries the programming signal to the storage device. The storage device stores the programming signal and an inverted programming signal which is the inverse of the programming signal. The selectable configuration circuit can be selectably configured to provide the programming signal or the inverted programming signal to a first input lead of the configuration control circuit. The configuration control circuit couples (or decouples) various elements of the FPGA in response to the signal provided on the first input lead.
In an alternate embodiment, the selectable configuration circuit is coupled between the input lead and the storage device. Again, the selectable configuration circuit can be selectably configured to provide the programming signal or the inverted programming signal to the first input lead of the configuration control circuit.
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Hoffman E. Eric
Hudspeth David R.
Xilinx , Inc.
Young Edel M.
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