Flexible phase-locked loop system to indicate...
Fully stable clock domain synchronization technique for...
Generation of pulse signals from a clock signal
Glitch detection circuit for outputting a signal indicative...
Global I/O timing adjustment using calibrated delay elements
Globally clocked interfaces having reduced data path length
Guaranteed edge synchronization for multiple clocks
Half-word synchronization method for internal clock
High latency timing circuit
High speed bus with alignment, re-timing and buffer...
High speed bus with alignment, re-timing and buffer...
High speed bus with alignment, re-timing and buffer...
High speed clock divider with synchronous phase start-up...
High speed data transfer synchronizing system and method
High speed interface device for reducing power consumption,...
High-speed data transfer synchronizing system and method
High-speed internal clock synchronizing method and circuit
High-speed phase-adjusted quadrature data rate (QDR)...
HVAC synchronization
Increasing robustness of source synchronous links by...