1000 mb phase picker clock recovery architecture using interleav
Accurate distributed system time of day
Accurate timing calibration for each of multiple high-speed...
Adaptive clock skew in a variably loaded memory bus
Adaptive data processing scheme based on delay forecast
Adaptive voltage scaling digital processing component and...
Adjustable byte lane offset for memory module to reduce skew
Adjustable byte lane offset for memory module to reduce skew
Adjustable data delay using programmable clock shift
Adjustable PCI asynchronous clock device
Adjustable timing circuit of an integrated circuit by...
Adjusting and measuring the timing of a data strobe signal...
Amplifier with a fan-out variable in time
Apparatus and method for asynchronously interfacing...
Apparatus and method for coordinating activities of one or...
Apparatus and method for detecting packet arrival time
Apparatus and method for device timing compensation
Apparatus and method for enhancing data transfer to or from...
Apparatus and method for generating a delayed clock signal
Apparatus and method for generating a delayed clock signal