Increasing robustness of source synchronous links by...

Details Increasing robustness of source synchronous links by... Increasing robustness of source synchronous links by...

2007-04-24

2007-04-24

Du, Thuan N. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S500000, C713S502000, C713S503000, C713S600000

Reexamination Certificate

active

10232157

ABSTRACT:
A source synchronous scheme in which data from one clock domain is synchronized to a clock of a second clock domain. Using a more reliable clock of the second domain to control and adjust the alignment after the data is latched in allows more robust performance to maintain correctly ordered data. In this manner, a write pointer based on strobe signal(s) from the first clock domain may be avoided.

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U.S. Patent Application entitled “Method and Apparatus for Detecting Strobe Errors”, U.S. Appl. No. 09/748,233 filed Dec. 27, 2000.
Bakoglu, H.B., Circuits, Interconections, and Packaging for VLSI, pp. 356-358.
W. J Dally & J.W. Poulton, Digital Systems Engineering, pp. 476-482.

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