Globally clocked interfaces having reduced data path length

Details Globally clocked interfaces having reduced data path length Globally clocked interfaces having reduced data path length

2005-11-01

2005-11-01

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S500000, C713S503000, C713S600000, C711S155000, C711S163000, C714S744000, C714S763000, C714S775000, C714S789000, C375S354000, C375S355000, C375S364000, C375S371000, C375S375000, C712S225000, C715S252000, C386S349000, C386S349000

Reexamination Certificate

active

06961861

ABSTRACT:
A interface, which connects memory and an integrated circuit, having a write path and read path that allow synchronous data propagation is provided. Further, a method for synchronizing data propagation through a read path and a write path of an interface is provided. The interface uses clock signals and paths based on a clock signal to synchronize the flow of data through various paths within the interface.

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patent: 2003/0105985 (2003-06-01), Keller et al.

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