High latency timing circuit

Details High latency timing circuit High latency timing circuit

2000-11-30

2004-05-04

Heckler, Thomas M. (Department: 2185)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C375S376000

Reexamination Certificate

active

06732286

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing circuit for synchronization of phase and frequency, and particularly to such a circuit having a highly pipelined structure, thereby optimizing the circuit for use in a high-speed read channel while inducing high latency.
2. Description of the Related Art
A clock and data recovery system, which may be referred to as a channel, invariably requires a timing recovery feedback loop for clock synchronization. Historically, this need has been fulfilled through the use of a phase-locked loop timing circuit. Phase-locked loop timing circuits typically include a frequency integration feedback loop and a phase integration feedback loop. They operate by first ascertaining the timing frequency and timing phase of the target signal, “locking” onto that frequency and phase, and then tracking deviations to both phase and frequency. The process of locking onto the timing frequency and timing phase is generally referred to as the acquisition mode, and the process of tracking deviations is generally referred to as the tracking mode. Phase-locked loop timing circuits are very well known in the literature and are the subject of many patents. For example, see U.S. Pat. Nos. 5,703,539; 5,727,038; 5,745,011; 5,754,607; 5,761,258; 5,793,824; 5,874,863; 5,889,829; 5,986,513; 5,987,085; 6,028,727; 6,066,988; and 6,084,480, the contents of each of which are incorporated herein by reference.
Typically, a frequency integration feedback loop includes a resistor and a capacitor connected in series, with the capacitor also connected to ground; and a phase integration feedback loop includes a voltage-controlled oscillator. The target signal, generally regarded as being an “error” signal because its phase and frequency require adjustment, is provided as input to the frequency integration feedback loop, and the output of that loop is provided as input to the phase integration feedback loop. Hence, the two loops generally operate jointly. However, the joint use of the two feedback loops reduces the stability of the overall circuit, as compared to the stability of each individual feedback loop. The stability of the overall circuit is inversely related to the speed at which the circuit is operated. In other words, if the circuit is operated at a sufficiently low speed, the circuit remains stable, but as the operation speed increases, the circuit tends to become unstable.
If a channel is to operated at a high speed, the feedback loop must be structured in a highly “pipelined” manner; i.e., more feedback elements must be present in the loop. This causes the loop to have a high latency, or time delay, associated with it. A high latency generally causes degraded performance of the timing loop, which in turn requires that the loop bandwidth be reduced in order to maintain loop stability. However, the timing acquisition must be accomplished in as short a time as possible, in order to maintain the speed of the channel and thereby not adversely impact overall system performance. Thus, a dilemma for implementation of high speed channels is presented.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the drawbacks noted above and provides a high speed timing recovery system with reduced latency.
In one aspect, the invention provides a digital phase locked loop (DPLL) circuit. The DPLL circuit includes a digital filter loop including a register, a digital voltage-controlled oscillator (VCO) responsive to the digital filter loop, and a phase shift measurement circuit responsive to the digital VCO. The register selectively receives an output of the phase shift measurement circuit for frequency offset correction. The DPLL circuit may be operable in an acquisition mode at a high bandwidth rate and in a tracking mode at a low bandwidth rate. When the DPLL circuit is operating in the acquisition mode at a high bandwidth rate, an input to the register may be set equal to zero to maintain DPLL circuit stability. The DPLL circuit may also include a phase interpolator and a synthesizer. The synthesizer may be used to generate a control signal. The phase interpolator may be used to receive an output signal of the phase shift measurement circuit and the generated control signal and use the received signals to calculate a frequency offset value.
In another aspect, the invention provides a phase locked loop circuit, including a digital filter loop for timing recovery. The circuit includes a phase synchronization feedback loop, a frequency synchronization feedback loop, and a phase shift measurement circuit. The phase shift measurement circuit includes a shift register. When an input to the frequency synchronization feedback loop is set to zero, the phase synchronization feedback loop is operated at a high bandwidth rate to synchronize phase and to compute a value of frequency offset using the shift register. Once the frequency offset has been computed, the input to the frequency synchronization feedback loop is set to the computed value of frequency offset, and the frequency synchronization feedback loop and the phase synchronization feedback loop are jointly operated at a low bandwidth rate to synchronize frequency and to track further deviations of phase or frequency. The use of a low bandwidth rate ensures circuit stability.
The phase locked loop circuit may also include a phase interpolator and a synthesizer. The synthesizer may generate a control signal. The phase interpolator may then receive an output signal of the voltage-controlled oscillator and the generated control signal, and use the received signals to calculate the frequency offset.
In yet another aspect of the invention, a digital loop filter for use as part of a phase locked loop includes a first integrator for frequency synchronization and a second integrator for phase synchronization. During a first synchronization period, the filter disables the first integrator and uses the second integrator to synchronize phase and calculate a frequency offset value. During a second synchronization period, the filter enables the first integrator and uses the calculated frequency offset value as an input to the first integrator to synchronize frequency. The filter may also include a phase interpolator for calculating the frequency offset value using a residual phase error that remains after phase is synchronized. The phase interpolator calculates the frequency offset value by measuring phase twice, subtracting the first measured value of phase from the second measured value of phase, and dividing the resultant difference by an elapsed time between the two measurements.
In still another aspect, a digital data acquisition loop is used with a phase interpolator. The loop includes a phase timing circuit having an overflow output, including a control signal. The control signal is provided to the phase interpolator, which outputs a frequency offset corresponding to the overflow output. The loop also includes a frequency timing circuit, which receives the frequency offset from the phase interpolator and adjusts the frequency timing of an input data stream based on the received frequency offset. The loop may also initially disable the frequency timing circuit during an acquisition period corresponding to the outputting of the frequency offset, and subsequently enable the frequency timing circuit during a tracking period that follows the outputting of the frequency offset. The loop may operate at a high speed during the acquisition period to ensure high performance, and at a low speed during the tracking period to ensure loop stability.
In a further aspect of the invention, a read channel for a hard disk drive includes a digital phase locked loop (DPLL) circuit. The DPLL circuit includes a digital filter loop comprising a register, a digital voltage-controlled oscillator (VCO) responsive to the digital filter loop, and a phase shift measurement circuit responsive to the digital VCO. The register selectively receives an output of the phase shift measurement circuit for frequency

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