Increasing robustness of source synchronous links by...
Independent timing compensation of write data path and read data
Information processing apparatus
Information processing apparatus and method of setting...
Information processing apparatus to control bus latency
Information processing device, method, and program
Input circuit and method for the operation thereof
Input signal phase compensation circuit capable of reliably obta
Integrated circuit and method for decorrelating an instruction s
Integrated circuit I/O using a high performance bus interface
Integrated circuit memory architecture with selectively...
Integrated circuit with timing adjustment mechanism and method
Integrated circuits and methods with transmit-side data bus...
Interactive device with time synchronization capability
Interface circuit using plurality of synchronizers for...
Interleaved delay line for phase locked and delay locked loops
Interleaved delay line for phase locked and delay locked loops
Interleaved delay line for phase locked and delay locked loops
Interlocked pipelined CMOS
Interlocked synchronous pipeline clock gating