High speed bus with alignment, re-timing and buffer...

Details High speed bus with alignment, re-timing and buffer... High speed bus with alignment, re-timing and buffer...

2007-12-06

2009-06-09

Patel, Nitin C (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S500000, C713S502000, C713S600000, C345S558000, C345S559000

Reexamination Certificate

active

07546480

ABSTRACT:
In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described. The invention is directed to a system for detecting either or both underflow and overflow of a circular buffer capable of holding n entries. The invention is also directed to a method of detecting either or both underflow and overflow of a circular buffer capable of holding n entries.

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