High speed clock divider with synchronous phase start-up...

Details High speed clock divider with synchronous phase start-up... High speed clock divider with synchronous phase start-up...

2006-01-31

2006-01-31

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S401000

Reexamination Certificate

active

06993671

ABSTRACT:
A system and method that controls the start time of different clocks in different clock domains, each of which is controlling an I/O, provides that the first cycle of each time domain is within a predetermined timing delay of one another. Reset signals are pipelined across the clock domains such that all the clocks trigger at substantially the same time. The clock channels may be arranged logically and physically in n groups of m channels with delays associated with each n group according to the relative position of the n group within the sequence of the n groups.

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