High speed bus with alignment, re-timing and buffer...

Details High speed bus with alignment, re-timing and buffer... High speed bus with alignment, re-timing and buffer...

2008-04-29

2008-04-29

Patel, Nitin C. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S500000, C713S502000, C713S600000, C713S400000, C345S558000, C345S559000, C365S233100

Reexamination Certificate

active

10405961

ABSTRACT:
In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described.

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Van Ess, D.,A Circular FIFO, PsoC Style, Cypress Microsystems, Application Note AN2036, Rev. B, pp. 1-5, Jun. 21, 2002.

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