Digital signal processor having data alignment buffer for perfor

Digital signal processor having distributed register file

Digital signal processor having enhanced utilization of...

Digital signal processor having multiple access registers

Digital signal processor particularly suited for decoding...

Digital signal processor with bit FIFO

Digital signal processor with cascaded SIMD organization

Digital signal processor with efficiently connectable...

Digital signal processor with variable width instructions

Digital signal processor with wait state register

Digital signal processors with configurable dual-MAC and...

Direct control of operation blocks using operand signal of...

Direct hardware processing of internal data structure fields

Direct memory access-based multi-processor array

Direct path monitoring by primary processor to each status...

Direct vectored legacy instruction set emulation

Directly accessing local memories of array processors for...

Distance controlled concatenation of selected portions of...

Distributed extensible processing architecture for digital signa

Distributed memory type information processing system