N-wide add-compare-select instruction
Native copy instruction for file-access processor with...
Near-orthogonal dual-MAC instruction set architecture with...
Nested parallel 2D Delaunay triangulation method
Network device including dedicated resources control plane
Network of parallel processors to faults-tolerant towards...
Network on chip with low latency, high bandwidth application...
Network processor system on chip with bridge coupling...
Network processor which makes thread execution control...
Network system with TCP/IP ACK reduction
Networked processor for a pipeline architecture
Next available buffer allocation circuit
Non-aligned double word fetch buffer
Non-blocking, multi-context pipelined processor
Non-copy shared stack and register file device and dual...
Non-destructive sideband reading of processor state information
Non-quick instruction accelerator including instruction identifi
Non-speculative instruction fetch in speculative processing
Non-stalling circular counterflow pipeline processor with reorde
Non-stalling circular counterflow pipeline processor with...