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N-wide add-compare-select instruction

Electrical computers and digital processing systems: processing – Processing control – Branching
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Native copy instruction for file-access processor with...

Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
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Near-orthogonal dual-MAC instruction set architecture with...

Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
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Nested parallel 2D Delaunay triangulation method

Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
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Network device including dedicated resources control plane

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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Network of parallel processors to faults-tolerant towards...

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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Network on chip with low latency, high bandwidth application...

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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Network processor system on chip with bridge coupling...

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
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Network processor which makes thread execution control...

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
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Network system with TCP/IP ACK reduction

Electrical computers and digital processing systems: processing – Architecture based instruction processing – Data flow based system
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Networked processor for a pipeline architecture

Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
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Next available buffer allocation circuit

Electrical computers and digital processing systems: processing – Architecture based instruction processing
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Non-aligned double word fetch buffer

Electrical computers and digital processing systems: processing – Instruction alignment
Patent

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Non-blocking, multi-context pipelined processor

Electrical computers and digital processing systems: processing – Processing control – Branching
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Non-copy shared stack and register file device and dual...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Non-destructive sideband reading of processor state information

Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
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Non-quick instruction accelerator including instruction identifi

Electrical computers and digital processing systems: processing – Architecture based instruction processing – Data flow based system
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Non-speculative instruction fetch in speculative processing

Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
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Non-stalling circular counterflow pipeline processor with reorde

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Patent

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Non-stalling circular counterflow pipeline processor with...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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