Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1999-08-04
2002-08-20
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C708S203000, C708S209000, C712S221000, C712S300000
Reexamination Certificate
active
06438676
ABSTRACT:
BACKGROUND
A. Technical Field
The invention relates to a data processor, a method of processing data and a method of compiling a program for a data processor.
B. Background of the Invention
Various signal processing applications use compressed data in which different signal values are represented by different numbers of bits. This is the case for example when Huffman coding is used.
When different numbers of bits are used, compression involves selecting the required number of bits from each signal value and placing the selected bits in a compressed word. Decompression involves taking the compressed word and obtaining decompressed signal values from selected groups of bits from the compressed words. The selection of a group for a number depends on the length of bits that has been used in the compressed word for the preceding numbers and on the length of bits used for the number itself.
Compression and decompression can be performed by a program that runs on a data processor. This will involve executing several instructions, for example for shifting register contents, combining register contents and masking undesired register contents.
PCT patent application WO 96/17289 describes a data processor that is capable of executing shift instructions that operate on registers that hold storage units made up of packed data. A register that contains packed data is organized into a number of equal length fields, for example four fields of sixteen bits. The data processor has an instruction set that contains a packed shift instruction for shifting a plurality of numbers by specified amounts. This shift instruction has two operands. A first operand contains several amount codes that specify a required amount of shift, each for a respective number in a second operand. The amount codes are stored as packed data in a first register and the numbers are stored as packed data in a second register. The processor generates a packed result, containing the various numbers from the second operand, each shifted by its own amount specified in the first operand. Thus, a single instruction can be used to cause the processor to execute a plurality of shift operations on different numbers.
The packed shift instruction may be used to reduce the number of instructions for variable length compression or decompression, but more than one instruction must still be used to compress or decompress a signal value.
Amongst others, it is an object of the invention to provide for a data processor which is capable of performing compression and/or decompression on packed data with fewer instructions.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the data processor is arranged as set forth in claim 1. Thus, the processor has a compression instruction which refers to two storage units, such as two operand registers, a first register containing one or more codes that specify relative amount(s) of shift that have to be applied to respective numbers in the second operand register. The relative amount(s) correspond for example to the lengths of bits to which respective numbers in a second operand register must be compressed. The numbers come from different fields in the second operand and the result may be placed in one of these fields or another field of a result operand. By using this instruction in programs for compressing data, the number of instructions needed for compression can be reduced. This saves execution time and reduces the memory space needed to store the program.
According to another aspect of the invention, the data processor is arranged as set forth in claim 2. Thus, the processor has a decompression instruction which refers to two storage units, such as two operand registers, a first register containing one or more length codes, which specify the lengths of bits to which respective numbers in a second operand register must be decompressed. By using this instruction in programs for decompressing data, the number of instructions needed for compression can be reduced. This saves execution time and reduces the memory space needed to store the program.
Some processors use different functional units for executing instructions from different subsets of the instruction set, such as VLIW (Very Long Instruction Word) processors, which contain for example one or more functional units for executing arithmetic/logic instructions, one or more functional units for executing shift instructions. These functional units may each be dedicated to one way of subdividing a register content into different fields, or multi-purpose, capable of handling several different subdivisions into fields. In a VLIW processor these different functional units may start executing different instructions, each from its own subset in parallel
According to another aspect of the invention, the instructions for placing the first and second group of bits is implemented using a functional unit for executing shift instructions. The shift circuits that are used for shifting the content of fields individually is used to shift the groups of bits in or from the same field.
REFERENCES:
patent: 5423010 (1995-06-01), Mizukawi
patent: 5859790 (1999-01-01), Sidwell
patent: 5951624 (1999-09-01), Gray et al.
patent: 6052769 (2000-04-01), Huff et al.
patent: 6098087 (2000-08-01), Lemay
patent: 6275834 (2001-08-01), Lin et al.
patent: WO9617289 (1996-06-01), None
patent: WO9732278 (1997-09-01), None
patent: WO9733222 (1997-09-01), None
Fenwick & West LLP
Kim Kenneth S.
TriMedia Technologies
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