Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
2011-01-18
2011-01-18
Petranek, Jacob (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C708S523000
Reexamination Certificate
active
07873815
ABSTRACT:
DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.
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Chen Xufeng
Hsu De D.
Lee Way-Shing
Sih Gilbert C.
Kamarchik Peter M.
Pauley Nicholas J.
Petranek Jacob
Qualcomm Incorporated
Velasco Jonathan T.
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