Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-02-04
2001-07-03
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S036000, C712S034000, C711S112000, C711S113000
Reexamination Certificate
active
06256724
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is digital signal processing and particularly a digital signal processor with a core data processor and a reconfigurable co-processor.
BACKGROUND OF THE INVENTION
Digital signal processing is becoming more and more common for audio and video processing. In many instances a single digital processor can replace a host of prior discrete analog components. The increase in processing capacity afforded by digital signal processors had enabled more types of devices and more functions for prior devices. This process has created the appetite for more complex functions and features on current devices and new types of devices. In some cases this appetite has outstripped the ability to cost effectively deliver the desired functionality with full programmable digital signal processors.
One response to this need is to couple a digital signal processor with an application specific integrated circuit (ASIC). The digital signal processor is programmed to handle control functions and some signal processing. The full programmability of the digital signal processor enables product differentiation through different programming. The ASIC is constructed to provide processing hardware for certain core functions that are commonly performed and time critical. With the increasing density of integrated circuits it is now becoming possible to place a digital signal processor and an ASIC hardware co-processor on the same chip.
This approach has two problems. This approach rarely results in an efficient connection between the hardware co-processor ASIC and the digital signal processor. It is typical to handle most of the interface by programming the digital signal processor. In many cases the digital signal processor must supply data pointers and commands in real time as the hardware co-processor is operating. To form safe designs, it is typical to provide extra time for the digital signal processor to service the hardware co-processor. This means that the hardware co-processor is not fully used. As second problem comes from the time to design problem. With the increasing capability to design differing functionality, the product cycles have been reduced. This puts a premium on designing new functions quickly. The ability to reuse programs and interfaces would aid in shortening design cycles. However, the fixed functions implemented in the ASIC hardware co-processor cannot be easily be reused. The typical ASIC hardware co-processor has a limited set of functions suitable for a narrow range of problems. These designs cannot be quickly reused even to implement closely related functions. In addition the interface between the digital signal processor and the ASIC hardware co-processor tends to use ad hoc techniques that are specific to a particular product.
SUMMARY OF THE INVENTION
This invention is a data processing system including a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor is responsive to commands from the digital signal processor core to perform predetermined data processing operations on data stored in said local memory in parallel with digital signal processor core. The data processing system includes a direct memory access circuit under the control of the digital signal processor core. The direct memory access circuit autonomously transfers data to and from the local memory of the co-processor.
The co-processor responds to commands to configure itself correspondingly to perform a set of related data processing operation. Co-processor commands are stored in a command first in first out memory. The command FIFO memory has an input mapped to a predetermined memory address.
The co-processor is responsive to various control commands. A receive data synchronism command pauses processing commands until the direct memory access circuit signals completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger a predetermined memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.
Each command includes an indication of a data input location within the local memory. The co-processor recalls data from local memory starting with the indicated data input location. Each command includes an indication of a data output location within the local memory. The co-processor stores resultant data in local memory starting with the indicated data output location. The input data may be stored in a circularly organized memory area serving as an input buffer. The resultant data may be stored in a circularly organized memory area serving as an output buffer.
REFERENCES:
patent: 5590204 (1996-12-01), Lee
patent: 5706013 (1998-01-01), Melvin et al.
patent: 5805536 (1998-09-01), Gage et al.
Gatherer Alan
Hocevar Dale E.
Hung Ching-Yu
Lemonds, Jr. Carl E.
Brady III W. James
Marshall, Jr. Robert D.
Pan Daniel H.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Digital signal processor with efficiently connectable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital signal processor with efficiently connectable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital signal processor with efficiently connectable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2519158