Electrical computers and digital processing systems: processing – Instruction decoding
Reexamination Certificate
2000-08-14
2002-04-02
Zimmerman, Mark (Department: 2671)
Electrical computers and digital processing systems: processing
Instruction decoding
C712S209000, C712S210000, C712S211000, C712S216000, C712S220000, C712S221000
Reexamination Certificate
active
06367003
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to architectures for digital signal processors. More particularly, the present invention relates to digital signal processors having both fixed and programmable functions.
2. Description of the Related Art
Digital signal processing involves the digital representation of signals and the use of digital processors (computers) to analyze, modify, or extract information from such signals. A Digital Signal Processor (DSP) is a computer processor in which the internal data paths and functional units of the processor have been optimized for executing the types of algorithms typically encountered in signal processing. A DSP is typically characterized by a multiple bus structure with separate memory spaces for data and program instructions and arithmetic units designed to perform multiply-accumulate operations very rapidly. As discussed in more detail below, the multiply-accumulate operation, or sum-of-products, involves the multiplication of two numbers to produce a result which is then added to a running sum of previous results. DSPs typically have a fast multiply-accumulator (MAC) functional unit which can perform the multiply and add (accumulate) operation in a single clock cycle.
Most DSP algorithms such as filtering, correlation and the Fast Fourier Transform (FFT) involve repetitive use of the MAC. The repetitive nature of these operations typically means that the operation of the processor falls into predictable patterns. This predictability of the algorithms allows the use of increased hardware parallelism in order to achieve high processing speeds. Predictability also allows a DSP designer to increase processor speed through the use of: a Harvard architecture; pipelining; special instructions dedicated to signal processing; replication of functional units; and an on-chip cache. In addition to the above features, many recent DSP designs have employed the use of Very Long Instruction Word (VLIW) architectures in an effort to provide additional hardware parallelism.
The use of a pipelined architecture allows the hardware in a DSP to provide the MAC with a continuous uninterrupted stream of data, and thus, in theory, the MAC can be kept busy all of the time. Nevertheless, for many signal processing applications, the MAC is not used during every processor cycle. In many cases, a signal processing. program running on the DSP program uses the MAC circuitry only occasionally, thus leaving the MAC idle and available for other uses much of the time. As described below, this inability to use the MAC continuously stems from the fact that, in addition to the multiply-accumulate operations, all signal processing programs must perform a variety of housekeeping functions such as input/output, branching, initializing variables, updating loop counter etc. Typically, these housekeeping functions do not require use of the MAC, thus leaving the MAC idle.
SUMMARY OF THE INVENTION
One aspect of the present invention is a DSP architecture in which a Multiply-Accumulator (MAC) is used for special fixed functions during times periods (“idle times”)when the programmable portions of the DSP are not using the MAC circuitry. During the idle times, the DSP processor gives control of the MAC to the fixed function circuit. The fixed functions provided by the fixed function circuit can include digital filters, including Finite Impulse Response (FIR) filters and Infinite Impulse Response (IIR) filters. The fixed functions may also include an oversampling filter associated with a sigma-delta converter, or any other function that manipulates digital data. The DSP may, under program control, load configuration registers for the fixed function, provide coefficients for a fixed function coefficient memory, or obtain results from the fixed function. Configuration data for the fixed function circuit may include the type of filter and the number of taps. For a decimation filter, the fixed function parameters can also include the decimation factor. Digital data sample values for the fixed function circuit may be stored in a sample memory, and filter coefficients (also know as filter weights) may be stored in a coefficient memory. A sigma-delta modulator may also be used to provide digital sample inputs to the fixed function circuit. In yet another embodiment, a sigma-delta modulator provides samples to a dedicated fast decimation filter. Output samples from the fast decimation filter are then provided to the fixed function circuit.
In another embodiment, the fixed function circuit may also operate in a “cycle steal” mode. In yet another embodiment, use of the MAC is allocated on a priority scheduling basis.
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Gazdzinski & Associates
Monestime Mackly
Zimmerman Mark
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