Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1998-07-14
2001-07-17
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S036000, C712S032000, C712S042000, C712S220000, C708S209000, C708S490000, C708S497000
Reexamination Certificate
active
06263420
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital signal processing and particularly to processing circuits for processing digital signals.
BACKGROUND OF THE INVENTION
A typical general purpose digital signal processor (DSP) includes a controller which decodes instructions, by controlling operations of a high speed data path, registers, and a memory address generator. Individual instructions are fetched to the controller, typically at the rate of one instruction per clock cycle (or slower), and the controller decodes each instruction and sends control signals to the data path, registers, and memory address generator to perform the actions required by the instruction. Through programmed combinations of instructions, any variety of data processing operations can be accomplished.
The high speed data path of a DSP typically includes a number of registers for storing data being processed, an arithmetic and logic unit (ALU) for performing logical (e.g., AND, OR, XOR) operations as well as arithmetic (addition, multiplication, division) operations, and a parallel-connected bit shifting unit for performing bit shifting and masking. The memory address generator, in response to the controller, generates memory addresses for retrieving data from a main memory for delivery to the DSP, or for storing data produced by the DSP. Often, the memory address generator must produce sequential addresses or addresses identifying equally spaced locations in memory, to achieve a desired pattern of information retrieval and storage.
Each DSP (or other microprocessor) is associated with a finite, well-defined set of instructions, which instructions are arranged into programs to operate the DSP. To provide an example, a typical DSP instruction identifies an operation to be performed by either the ALU or bit shifting unit, identifies source register(s) in the DSP containing values on which the operation is to be performed, and identifies destination register(s) where the results of the operation are to be stored. In some cases the instruction may incorporate binary data to be used as one operand for the instruction, in which case the binary data incorporated in the instruction is delivered to the data path and combined with data stored in the registers by the ALU or bit shifting unit.
A typical calculation might be performed as follows: The memory address generator obtains values from main memory for processing. Once retrieved, the ALU performs a numeric operation on the values, and the results are fed back into registers. The results in the registers are then fed into the bit shifting and masking unit during a next instruction cycle. Finally, the memory address generator causes the processed values to be stored back in the main memory.
SUMMARY OF THE INVENTION
In accordance with principles of the present invention, a DSP is provided with processing circuitry particularly adapted for decoding digital audio. Specifically, a barrel shifter is enhanced to perform the logical operations typically performed in an ALU, so that operations involving a combination of a logical operation and a shift, can be performed in a single pass through the combined barrel shifter/logical unit, rather than requiring separate passes through the barrel shifter and ALU, which would require more instruction cycles.
One particular operation which combines a logical operation and shift, is a cyclic redundancy check. Another particular operation is the unpacking of a bit stream. Both operations are often used in digital signal decoding, and particular instructions for facilitating these operations are described.
In accordance with another aspect, the DSP is improved by reducing the number of instruction cycles needed for the memory generation unit to generate an address within a table, using an index and base address. Specifically, the address generator concatenates the most significant bits of the base address of a table to the least significant bits of the index into the table.
In specific disclosed embodiments, the address generator unit includes an adder for incrementing or decrementing the index in response to instructions. Further, the address generator includes a limiter coupled to the output of the adder for preventing the index from being incremented to a value greater than the length of the table, or decremented to a value below zero.
The above and other objects and advantages of the present invention shall be made apparent from the accompanying drawings and the description thereof.
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Fukushima Tetsuya
Ozeki Agee
Tan Yew-Koon
An Meng-Al T.
Lin Wen-Tai
Sony Corporation
Wood, Herron&Evans, L.L.P.
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