Unhandled operation handling in multiple instruction set...
Unified buffer for tracking disparate long-latency...
Unified memory architecture for use by a main processor and...
Unified multi-function operation scheduler for out-of-order...
Unified renaming scheme for load and store instructions
Unified shared pipeline allowing deactivation of RISC/DSP...
Uniform register addressing using prefix byte
UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN...
Universal dependency vector/queue entry
Universal dependency vector/queue entry
Universal load address/value prediction using stride-based...
Universal pointer implementation scheme for uniformly...
Universal register rename mechanism for instructions with...
Unprivileged context management
Update forwarding cache for address mode
Updating condition status register based on instruction...
Updating stack pointer based on instruction bit indicator...
Use of a future file for data address calculations in a...
Use of a neutral instruction as a dependency indicator for a...
Use of enable bits to control execution of selected...