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Unhandled operation handling in multiple instruction set...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Unified buffer for tracking disparate long-latency...

Electrical computers and digital processing systems: processing – Instruction issuing
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Unified memory architecture for use by a main processor and...

Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
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Unified multi-function operation scheduler for out-of-order...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Unified renaming scheme for load and store instructions

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Unified shared pipeline allowing deactivation of RISC/DSP...

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
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Uniform register addressing using prefix byte

Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
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UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN...

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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Universal dependency vector/queue entry

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Universal dependency vector/queue entry

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Universal load address/value prediction using stride-based...

Electrical computers and digital processing systems: processing – Processing control – Branching
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Universal pointer implementation scheme for uniformly...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Universal register rename mechanism for instructions with...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Unprivileged context management

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
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Update forwarding cache for address mode

Electrical computers and digital processing systems: processing – Architecture based instruction processing – Stack based computer
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Updating condition status register based on instruction...

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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Updating stack pointer based on instruction bit indicator...

Electrical computers and digital processing systems: processing – Architecture based instruction processing – Stack based computer
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Use of a future file for data address calculations in a...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Use of a neutral instruction as a dependency indicator for a...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Use of enable bits to control execution of selected...

Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
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