Distributed extensible processing architecture for digital signa

Details Distributed extensible processing architecture for digital signa Distributed extensible processing architecture for digital signa

1998-10-26

2000-03-21

Treat, William M.

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

712 20, 712 21, 712 22, G06F 1900

Patent

active

060414006

ABSTRACT:
A circuit arrangement and method utilize a distributed extensible processing architecture to allocate various DSP functions or operations between multiple processing cores disposed on an integrated circuit device. Each processing core includes one or more hardwired datapaths to provide one or more DSP operations. Moreover, each processing core includes a programmable controller that controls the operation of each hardwired datapath via a local computer program executed by the controller. Furthermore, the processing cores are coupled to one another over a communications bus to permit data to be passed between the cores and thereby permit multiple DSP operations to be performed on data supplied to the device.

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Egura et al., "An 800 MOPS 110 mW 1.5 V Parallel DSP for Mobile Multimedia Processing", 1998 IEEE International Solid-State Circuits Conference, pp. 292-293.
Crinon, Regis I., "ATSC Data Broadcast Services: Protocols, Application Signaling, Buffer Models, Profiles, and Levels", ICCE., International Conference on Consumer Electronics, IEEE, pp. 4-5, Jun. 22-24 1999.
Ibrahim et al., "An Enhanced DSP Architecture for the Seven Multimedia Functions: the Mpact 2 Processor", IEEE Workshop on Signal Processing Systems, 1997 SIPS97--Design and Implementation, pp. 76-85, Nov. 3-5,1997.
Muroda et al., "Multimedia Processors," Proceedings of the IEEE, vol. 86, iss. 6, pp. 1203-1221, Jun. 1998.

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