Digital signal processor with variable width instructions

Electrical computers and digital processing systems: processing – Processing control – Mode switch or change

Reexamination Certificate

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Details

C712S024000, C712S043000, C712S204000

Reexamination Certificate

active

06189090

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to digital signal processing and particularly to processing circuits for processing digital signals.
BACKGROUND OF THE INVENTION
A typical general purpose digital signal processor (DSP) includes a controller which decodes instructions, by controlling operations of a high speed data path, registers, and a memory address generator. Individual instructions are fetched to the controller, typically at the rate of one instruction per clock cycle (or slower), and the controller decodes each instruction and sends control signals to the data path, registers, and memory address generator to perform the actions required by the instruction. Through programmed combinations of instructions, any variety of data processing operations can be accomplished.
Each DSP (or other microprocessor) is associated with a finite, well-defined set of equal-length instructions, which instructions are arranged into programs to operate the DSP. The number and length of the instructions, and the operations they perform, varies from one DSP to another based on the functions desired. For example, some DSPs support a relatively large set of relatively long (e.g., 32-bit) instructions allowing the choice of many different functions; other DSPs support only a small set of relatively short (e.g., 16-bit) instructions providing a choice of fewer functions. Instruction size and complexity are proportional. Larger instructions can identify functions with more specificity than smaller instructions, thus allowing more complex functions to be completed within each instruction cycle. Larger instructions, however, require more memory space to store. Since all instructions are the same size, increasing the size of one instruction causes a proportionate increase in the size of every other instruction, and thus a proportionate increase in the size of all programs for the DSP, even if only a small fraction (or none) of the instructions in a given program make use of the complex operations which necessitated the increased instruction size.
SUMMARY OF THE INVENTION
In accordance with principles of the present invention, a DSP supports an instruction set including both 16-bit instructions and 32-bit instructions, so that particular portions of a program requiring only 16-bit instructions may be encoded in a 16-bit mode, thus reducing the program memory needed to store these portions.
In particular embodiments of this aspect, the DSP switches between the 16- and 32-bit modes only in response to flow control instructions such as JUMP, CALL or RETURN instructions. These instructions require flushing the instruction pipelines in the DSP, and thus are useful times to switch instruction modes. JUMP and CALL instructions are coded to indicate the processor mode applicable to the instructions to which the JUMP or CALL instruction goes to, so that the processor may change modes as needed when executing the JUMP or CALL instruction. When a CALL is executed the current processor mode is stored on the processor's stack, so that in response to a RETURN instruction the processor can return to this mode by retrieving the stored mode from the stack.
Further aspects of the present invention include the method of controlling operations of the DSP in response to short and long instructions, and a method of assembling a source program of code lines into modules of short and long instructions, and linking the modules into an object program.
The above and other objects and advantages of the present invention shall be made apparent from the accompanying drawings and the description thereof.


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