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Safety net paradigm for managing two computer execution modes

Electrical computers and digital processing systems: processing – Processing architecture – Vector processor
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Saving and restoring architectural state for processor cores

Electrical computers and digital processing systems: processing – Processing control – Branching
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Saving/restoring task state data from/to device controller...

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
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Scalable and configurable execution pipeline of handlers...

Electrical computers and digital processing systems: processing – Architecture based instruction processing – Data flow based system
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Scalable and configurable multimedia system for a vehicle

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
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Scalable hypercube multiprocessor network for massive...

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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Scalable link stack control method with full support for...

Electrical computers and digital processing systems: processing – Processing control – Branching
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Scalable processor

Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
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Scalar hardware for performing SIMD operations

Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
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Scalar result producing method in vector/scalar system by...

Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
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Scalar result producing method in vector/scalar system by...

Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
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Scaleable array of micro-engines for waveform processing

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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Scan chains for out-of-order load/store execution control

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Scannable zero-catcher and one-catcher circuits for reduced...

Electrical computers and digital processing systems: processing – Processing architecture
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Scheduler capable of issuing and reissuing dependency chains

Electrical computers and digital processing systems: processing – Instruction issuing
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Scheduler for use in a microprocessor that supports...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Scheduler reducing cache failures after check points in a comput

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
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Scheduler which discovers non-speculative nature of an...

Electrical computers and digital processing systems: processing – Instruction issuing
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Scheduler which retries load/store hit situations

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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Scheduling instructions in a cascaded delayed execution...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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