Safety net paradigm for managing two computer execution modes
Saving and restoring architectural state for processor cores
Saving/restoring task state data from/to device controller...
Scalable and configurable execution pipeline of handlers...
Scalable and configurable multimedia system for a vehicle
Scalable hypercube multiprocessor network for massive...
Scalable link stack control method with full support for...
Scalable processor
Scalar hardware for performing SIMD operations
Scalar result producing method in vector/scalar system by...
Scalar result producing method in vector/scalar system by...
Scaleable array of micro-engines for waveform processing
Scan chains for out-of-order load/store execution control
Scannable zero-catcher and one-catcher circuits for reduced...
Scheduler capable of issuing and reissuing dependency chains
Scheduler for use in a microprocessor that supports...
Scheduler reducing cache failures after check points in a comput
Scheduler which discovers non-speculative nature of an...
Scheduler which retries load/store hit situations
Scheduling instructions in a cascaded delayed execution...