Back-end renaming in a continual flow processor pipeline

Background completion of instruction and associated fetch reques

Backing out of a processor architectural state

Backing Register File for processors

Backing store buffer for the register save engine of a...

Backplane system having high-density electrical connectors

Backup redundant routing system crossbar switch architecture...

Banked shadowed register file

Barrier synchronization mechanism for processors of a...

Barrier synchronization method, device, and multi-core...

Basic block cache microprocessor with instruction history...

Basic block oriented trace cache utilizing a basic block...

Bi-directional return register stack recovery from...

Bi-level branch target prediction scheme with fetch address pred

Bi-level branch target prediction scheme with mux select predict

Bidirectional communication port for digital signal processor

Bit field extraction with sign or zero extend

Bit field extraction with sign or zero extend

Bit field processor

Bit manipulation instructions