Accumulator read port arbitration logic

Details Accumulator read port arbitration logic Accumulator read port arbitration logic

1997-11-14

2001-01-16

Treat, William M. (Department: 2783)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C708S631000, C708S632000

Reexamination Certificate

active

06175912

ABSTRACT:

FIELD OF THE INVENTION
The invention pertains to the architecture of processors. More particularly, the invention pertains to communication data paths between an accumulator and other data processing and storage units in a digital signal processor.
BACKGROUND OF THE INVENTION
Digital signal processors (DSPs) include an accumulator for temporarily storing data generated by the one or more data processing units in the DSP. Commonly, the accumulator comprises multiple storage locations for simultaneously storing multiple, separate, pieces of data. Such an accumulator might be comprised of a register file. Sometimes each separate storage location in a processor core is termed an accumulator and thus, under this terminology, the processing core comprises many separate accumulators. In this specification, all temporary storage locations in a processor core are collectively termed an accumulator and each individually accessible storage location is termed an accumulator register.
The data processing units in the DSP, for example, may comprise one or more of each of an arithmetic logic unit (ALU), a bit manipulation unit (BMU), a multiply and accumulate unit (MAC), an adder, etc. Instructions in the instruction set of a DSP commonly call for the value generated at the output of one or more of the data processing units to be stored to one of the registers in the accumulator. Another instruction may call for data stored in one or more of the accumulator registers to be read out to the input of one or more of the data processing units to be used in the generation of further data by the data processing unit. Even further, instructions may call for data stored in one or more accumulator registers to be read out to memory via a data bus. A single instruction may even include a combination of two or more of any of the aforementioned operations. In order for the use of multiple data processing units in a DSP to be efficient, the accumulator must have multiple read ports and multiple write ports so that the multiple pieces of data needed to execute an instruction and/or the multiple pieces of data generated as a result of the execution of an instruction can all be written to and/or read from the accumulator during the execution of the instruction.
From a chip area perspective, read and write ports for an accumulator consume large amounts of chip area. Accordingly, an increase in the number of accumulator read and/or write ports in a DSP significantly increases the required size of the DSP data path. Further, as the number of read or write ports of an accumulator increases, the access time for the accumulator also increases. Thus, as the number of accumulator read and write ports increases, a slower and slower clock speed must be used, since the read access time will be in a timing critical path in virtually all practical DSPs.
Depending on the complexity of the DSP and the instruction set, a single instruction may call for the writing of multiple pieces of data to different registers in the accumulator as well as the reading out of the data from multiple registers in the accumulator to different destinations, such as an input of one of the data processing unit or memory.
Accordingly, it is an object of the present invention to reduce the number of read ports of an accumulator in a processor without any loss in functionality.
It is another object of the present invention to provide an improved digital signal processor.
It is another object of the present invention to provide a faster digital signal processor.
It is a further object of the present invention to provide a smaller digital signal processor without loss in functionality.
It is yet another object of the present invention to provide a less expensive digital signal processor without loss in functionality.
SUMMARY OF THE INVENTION
The invention is a processor, preferably a digital signal processor, having a multi-port accumulator register file having read and/or write ports that are shared among a plurality of data destinations and/or sources, respectively. The accumulator register file has multiple write ports and multiple read ports. One or more of the read ports is coupled to an input of one or more of the data processing units in the DSP as well as to another data destination, e.g., a data bus. Thus, each such shared read port may alternately be used to read data from an accumulator register to an input of one of the data processing units or to the bus. The bus may be coupled to memory or any other data destination. The write ports are coupled to receive data from various data processing units, such as an ALU and a BMU, and may be shared among the data processing units and a data bus or other data source in the same manner as described above with respect to the read ports.
An instruction sub-decoder receives each instruction (or a subset of the bits in the instruction) and decodes them to generate control lines for operating the accumulator to select which accumulator register is coupled with which read or write port during the execution of that instruction in accordance with the necessary read and/or write operations for that instruction.
By sharing the accumulator read and write ports, the number of necessary read and write ports to accommodate direct communication between the accumulator and the multiple various data sources and destinations is reduced. For instance, a given read port can be used during certain instructions to read data from an accumulator register to an input of a data processing unit in the DSP core, while during another instruction, the same read port can be used to read data out to memory (via the bus, for example).
In this manner, a separate port need not be dedicated to every particular data source or destination. Rather, one or more of the read ports can be coupled to multiple data destinations and one or more of the write ports can be coupled to multiple data sources. The ports are configurable on the fly and different instructions can utilize each port to communicate with a data destination or source different from the data destination or source that another instruction uses that port to communicate with.


REFERENCES:
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patent: 4323964 (1982-04-01), Gruner
patent: 5005150 (1991-04-01), Dent et al.
patent: 5784306 (1998-07-01), Ogletree
T.K.M. Agerwala, “Accumulator-Based Vector Instructions”,IBM Technical Disclosure Bulletin, vol. 24, No. 5, pp. 2483-2489, Oct. 1981.

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