Aggressive store merging in a processor that supports...

Details Aggressive store merging in a processor that supports... Aggressive store merging in a processor that supports...

2011-04-26

2011-04-26

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Reexamination Certificate

active

07934080

ABSTRACT:
Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.

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