Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
2011-05-03
2011-05-03
Li, Aimee J (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S222000
Reexamination Certificate
active
07937568
ABSTRACT:
A method, system and processor for increasing the instruction throughput in a processor executing longer latency instructions within the instruction pipeline. Logic associated with specific stages of the execution pipeline, responsible for executing the particular type of instructions, determines when at least a threshold number of the particular-type instructions is scheduled to be executed. The logic then automatically changes an execution cycle frequency of the specific pipeline stages from a first cycle frequency to a second, pre-established higher cycle frequency, which enables more efficient execution and higher execution throughput of the particular-type instructions. The cycle frequency of only the one or more functional stages are switched to the higher cycle frequency independent of the cycle frequency of the other functional stages in the processor pipeline. The logic also automatically switches the execution cycle frequency of the specific pipeline stages back from the second, higher cycle frequency to the first cycle frequency, when the number of scheduled first-type instructions has completed execution.
REFERENCES:
patent: 3656123 (1972-04-01), Carnevale et al.
patent: 5309561 (1994-05-01), Overhouse et al.
patent: 5420808 (1995-05-01), Alexander et al.
patent: 5844830 (1998-12-01), Gorshtein et al.
patent: 5987617 (1999-11-01), Hu et al.
patent: 5996083 (1999-11-01), Gupta et al.
patent: 6101596 (2000-08-01), Tanaka et al.
patent: 6163837 (2000-12-01), Chan et al.
patent: 6279100 (2001-08-01), Tremblay et al.
patent: 6446029 (2002-09-01), Davidson et al.
patent: 6477654 (2002-11-01), Dean et al.
patent: 6487675 (2002-11-01), Sager et al.
patent: 6715090 (2004-03-01), Totsuka et al.
patent: 6996701 (2006-02-01), Shimamura
patent: 7243217 (2007-07-01), Oliver
patent: 7287173 (2007-10-01), Hsieh
patent: 7523339 (2009-04-01), Shinkawa
patent: 2002/0038418 (2002-03-01), Shimamura
patent: 2002/0184543 (2002-12-01), Wingen
patent: 2004/0243866 (2004-12-01), Sherburne, Jr.
patent: 2005/0138450 (2005-06-01), Hsieh
patent: 2005/0166073 (2005-07-01), Lee
patent: 2005/0262374 (2005-11-01), Shinkawa
patent: 2006/0080566 (2006-04-01), Sherburne, Jr.
patent: 2007/0143757 (2007-06-01), Chiba
Correale, Jr. Anthony
Tsuchiya Kenichi
Dillon & Yudell LLP
International Business Machines - Corporation
Li Aimee J
LandOfFree
Adaptive execution cycle control method for enhanced... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Adaptive execution cycle control method for enhanced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adaptive execution cycle control method for enhanced... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2649754