Accuracy of multiple branch prediction schemes

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

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Reexamination Certificate

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06948055

ABSTRACT:
A method and apparatus of improving prediction accuracy of a branch instruction scheme includes reading an individual instruction in a current set of instructions, fetching the individual instruction when an instruction fetch unit determines that the individual instruction is valid, and allowing the instruction fetch unit to use an index address for the fetched individual instruction. A method and apparatus of improving branch prediction accuracy includes receiving a set of instructions having an assigned address, making a prediction for a branch instruction in the set of instructions using the assigned address, and retaining the assigned address for the branch instruction in the set of instructions.

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patent: 5434985 (1995-07-01), Emma et al.
patent: 5805878 (1998-09-01), Rahman et al.
patent: 0 605 876 (1994-07-01), None
PCT International Search Report, May 15, 2002, 5 pages.
Yeh, Tse-Yu and Patt, Yale, N., “A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History”, Department of Electrical Engineering and Computer Science, The University of Michigan; pp. 257-266, Undated.
Wallace, Steven and Bagerzadeh, Nader, “Multiple Branch and Block Prediction”, Department of Electrical and Computer Engineering, University of California, Irvine; pp. 1-10, Undated.

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