Generating interface adjustment signals in a...
Generating mask layout data for simulation of lithographic...
Generating mask patterns for alternating phase-shift mask...
Generating optimized and secure IP cores
Generating self-checking test cases from a reduced case...
Generating self-checking test cases from a reduced case...
Generating standard delay format files with conditional path...
Generation of a circuit design from a command language...
Generation of a hardware interface for a software procedure
Generation of a specification of a network packet processor
Generation of a specification of a processor of network packets
Generation of clock gating function for synchronous circuit
Generation of design views having consistent input/output...
Generation of engineering change order (ECO) constraints for...
Generation of graphical congestion data during placement...
Generation of graphical design representation from a design...
Generation of metal holes by via mutation
Generation of ordered interconnect output from an HDL...
Generation of refined switching windows in static timing...
Generation of refined switching windows in static timing...