Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-11
2010-12-07
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07849425
ABSTRACT:
A method, system and apparatus for constructing a comprehensive test plan for a design under test (DUT) using a hierarchy of goals to generate test cases are provided. Embodiments of the present invention provide for automatically generating a first test case of the test plan from the goal hierarchy by traversing a path from a starting goal to an ending goal, wherein a first goal in the path has a first definition for one or more of a slot and a method. The ending goal of will then assume the first definition of the slot or method, as needed. A further aspect of the invention is generating a second test case by traversing a second path through the hierarchy. If the second path involves traversing a second goal with a second definition of the slot or method, then the ending goal will assume the second definition of the slot or method, as needed.
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Flatau Arthur D.
Hamid Adnan A.
Breker Verification Systems, Inc.
Campbell Stephenson LLP
Geld Jonathan N.
Lin Sun J
Memula Suresh
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