&egr;-discrepant self-test technique
(Design rule check)/(electrical rule check) algorithms using...
2-dimensional placement with reliability constraints for...
2.5-D graph for multi-layer routing
4K derating scheme for propagation delay and setup/hold time...
7-tracks standard cell library
Abstracting netlist to manage routing information
Abstraction refinement using controllability and...
Accelerated design optimization
Accelerated layout processing using OPC pre-processing
Accelerating high-level bounded model checking
Accelerating PCB development and debug in advance of...
Accelerating PCB development and debug in advance of...
Access cell design and a method for enabling automatic...
Access cell design and a method for enabling automatic...
Accounting for the effects of dummy metal patterns in...
Accuracy of timing analysis using region-based voltage drop...
Accurate and realistic corner characterization of standard...
Accurate density calculation with density views in layout...
Accurate layout modeling for centerline-based detail routing