Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-06-14
2010-02-23
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07669166
ABSTRACT:
A method for generating a hardware description language (HDL) specification of a processor of network packets. Independent sets of interdependent handlers are determined from a specification of the handlers for processing the network packets. Either a first pipeline or a cluster of threads is selected for a corresponding architecture for each independent set. The corresponding architecture has one or more concurrent units for each interdependent handler in the independent set. Each concurrent unit is either a stage of the first pipeline or a thread of the cluster. Each action of each interdependent handler in each independent set is assigned to a concurrent unit for the interdependent handler. Each of these actions is also assigned to a stage of a second pipeline for the concurrent unit. The HDL specification of the processor is generated specifying the corresponding architecture for each independent set and the second pipeline for each concurrent unit.
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Attig Michael E.
Brebner Gordon J.
Cartier Lois D.
Garbowski Leigh Marie
Maunu LeRoy D.
Xilinx , Inc.
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