Generation of metal holes by via mutation

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

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10703100

ABSTRACT:
A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

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Kahng, A.B. et al., “Filling Algorithms and Analyses for Layout Density Control”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, No. 4, Apr. 1999, pp. 445-462.

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