Generation of graphical design representation from a design...

Details Generation of graphical design representation from a design... Generation of graphical design representation from a design...

2006-07-06

2008-08-12

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07412669

ABSTRACT:
Method and apparatus are described for generating a block diagram of an electronic circuit design. In one embodiment, each instance of a multi-master bus, a bus master of a multi-master bus, a bus slave of a multi-master bus, a memory, a co-processor and an input/output port is are identified. Instances of input/output ports are placed about a perimeter of a first area of the diagram. Each instance of a multi-master bus is placed in a bus area within the first area and each bus master is placed in a master area. The bus slaves of a bus are collected in a group, and the group is placed as a single block in a slave area within the first area. The group of bus slave slaves is aligned with a bus master. A diagrammatic representation is output consistent with the placement representations.

REFERENCES:
patent: 6189061 (2001-02-01), Katz et al.
patent: 6772254 (2004-08-01), Hofmann et al.
patent: 6917998 (2005-07-01), Giles
patent: 7032061 (2006-04-01), Huch et al.
patent: 7145903 (2006-12-01), Gutierrez
U.S. Appl. No. 11/405,894, filed Apr. 18, 2006, Tetzlaff.

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