Sample probability of fault function determination using...
Sanity checker for integrated circuits
Saturation region transistor modeling for geometric programming
Scalable and parallel processing methods and structures for...
Scalable and parallel processing methods and structures for...
Scalable logic self-test configuration for multiple chips
Scalable mesh architecture with reconfigurable paths for an...
Scalable parallel test bus and testing method
Scalable scan-path test point insertion technique
Scalable, partitioning integrated circuit layout system
Scale-invariant topology and traffic allocation in...
Scaleable approach to extracting bridges from a...
Scaling method for a digital photolithography system
Scan cell including a propagation delay and isolation element
Scan chain modification for reduced leakage
Scan chain verification using symbolic simulation
Scan compression circuit and method of design therefor
Scan design for double-edge-triggered flip-flops
Scan diagnosis system and method
Scan insertion with bypass login in an IC design