Generation of ordered interconnect output from an HDL...

Details Generation of ordered interconnect output from an HDL... Generation of ordered interconnect output from an HDL...

2005-03-15

2005-03-15

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06868531

ABSTRACT:
Techniques are described for generating and presenting interconnection information for a circuit in a manner that allows a designer to more easily validate the interconnectivity of the circuit. For example, a system comprises a computer-readable medium to store data that defines a circuit in accordance with a hardware description language. An interconnect analysis module processes the data to identify instances of circuit components having interconnects, and any signals coupled to the interconnects. The output includes an ordered representation of the interconnects, and specifies for each interconnect a respective signal associated with the interconnect and the other interconnects coupled to the signal. The output may be arranged to order the representation based on page numbers of schematic diagrams with which the instances are associated. The interconnect analysis module may generate the output in a two-dimensional format having rows and columns suitable for display in a spreadsheet application.

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