Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-12
2002-09-17
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06453451
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to electronic circuit design using computer simulation techniques. More specifically, but without limitation thereto, the present invention relates to back-annotating Standard Delay Format files used by logic design tools to simulate a variety of operating conditions for an integrated circuit design.
In previous methods for modeling delays in an integrated circuit design, software tools for generating delays include an IOPATH delay parameter which may be globally back-annotated by the system designer for the best case, the typical case, and the worst case delay values. For a conditional path delay, or a moded delay path, the back-annotated value depends on the mode in which the design is being simulated. Based on the mode, the values for the best case delays or the worst case delays have to be manually back-annotated, which may be an extremely time-consuming and error-prone process.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the needs above as well as other needs by providing a method of generating back-annotated Standard Delay Format (SDF) files for use by logic design tools in simulating the operation of an integrated circuit design under a variety of operating conditions with conditional/moded delays.
In one embodiment, the invention may be characterized as a method of generating a back-annotated Standard Delay Format file for designing integrated circuits that includes the steps of receiving as inputs a main input file, a conditional delay specifications file, and a selected option switch; inserting delay information from the conditional delay specifications file for each cell entry in the main input file according to the selected option switch into an output data structure; and generating the back-annotated Standard Delay Format file from the output data structure.
In another embodiment, the invention may be characterized as a computer program product that includes a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform the following functions: receiving as inputs a main input file, a conditional delay specifications file, and a selected option switch; inserting delay information from the conditional delay specifications file for each cell entry in the main input file according to the selected option switch into an output data structure; and generating the back-annotated Standard Delay Format file from the output data structure.
The features and advantages summarized above in addition to other aspects of the present invention will become more apparent from the description, presented in conjunction with the following drawings and Appendix.
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patent: 6405356 (2002-06-01), Yang
Dalton Kenton
Lakshmanan Viswanathan
Fitch Even Tabin & Flannery
LSI Logic Corporation
Phan Trong
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