Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-06-14
2009-12-22
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07636908
ABSTRACT:
Methods are provided for generating a hardware description language (HDL) specification of a network packet processor from a first, second, and third specification. The first specification specifies at least one handler of the network packet processor for processing input network packets and producing output network packets. Each handler processes a corresponding type of network packets and includes one or more actions for inspecting and modifying fields of the corresponding type of network packets. The second specification specifies a plurality of characteristics of a plurality of ports of the network packet processor. The characteristics include respective data widths of the ports. The ports include one or more input ports for receiving the input network packets and one or more output ports for transmitting the output network packets. The third specification specifies one or more behavioral constraints of the network packet processor.
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Cartier Lois D.
Garbowski Leigh Marie
Maunu LeRoy D.
Xilinx , Inc.
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